Proceedings of the 22nd EUROMICRO Conference Implementation of Processor Cells for Array Algorithms on FPGAs Prague, Czech Republic September 02-September 05 ISBN: 0-8186-7487-3
Abstract: Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal "jigsaw tessellated" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.
Index Terms:
field programmable gate arrays; FPGA; array algorithms; processor cells; fine-grain array architectures; processor arrays; cellular image processing algorithms; placement-routing tool
Citation:
I. Vassanyi, I. Erenyi, "Implementation of Processor Cells for Array Algorithms on FPGAs," euromicro, pp.0046, Proceedings of the 22nd EUROMICRO Conference, 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||