Abstract: In multivector processors, the effective throughput of the memory system is a decisive factor in the performance of the system. The lost cycles due to conflicts between concurrent vector streams make the effective throughput be lower than the peak throughput. When the request rate of all the concurrent vector streams to every memory module is less than or equal to the service rate, conflicts appear because concurrent vector streams reference memory modules in different orders. This paper proposes an access sequence to the vector stream elements that eliminates this kind of conflicts, allowing the effective throughput reach the peak throughput. In other cases, when request rate is greater than the service rate, the proposed order reduces the number of lost cycles, and the effective throughput increases.