Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip

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	Similar Articles Articles by Jörg Langeheine Articles by Karlheinz Meier Articles by Johannes Schemmel

2002 NASA/DoD Conference on Evolvable Hardware (EH'02)

Alexandria, Virginia

July 15-July 18

ISBN: 0-7695-1718-8

	ASCII Text	x
	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, "Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip," Evolvable Hardware, NASA/DoD Conference on, pp. 75, 2002 NASA/DoD Conference on Evolvable Hardware (EH'02), 2002.

	BibTex	x
	@article{ 10.1109/EH.2002.1029869, author = {Jörg Langeheine and Karlheinz Meier and Johannes Schemmel}, title = {Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip}, journal ={Evolvable Hardware, NASA/DoD Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1718-8}, pages = {75}, doi = {http://doi.ieeecomputersociety.org/10.1109/EH.2002.1029869}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Evolvable Hardware, NASA/DoD Conference on TI - Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip SN - 0-7695-1718-8 SP EP A1 - Jörg Langeheine, A1 - Karlheinz Meier, A1 - Johannes Schemmel, PY - 2002 KW - null VL - 0 JA - Evolvable Hardware, NASA/DoD Conference on ER -

Jörg Langeheine, Heidelberg University

Karlheinz Meier, Heidelberg University

Johannes Schemmel, Heidelberg University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EH.2002.1029869

In this paper the results of a series of intrinsic hardware evolution experiments with a CMOS FPTA chip are presented. The experiments discussed are restricted to the evolution of specified target DC behaviors. In the first series of experiments the evolution of different logic gates, namely NAND, NOR, AND, OR and XOR, is studied. The success rates in evolving the different logic gates are compared to each other. Furthermore the influence of three different methods of presenting the test patterns to the chip is analyzed. In a second series of experiments the evolution of a Gaussian voltage transfer characteristic is tackled. Thereby the influence of the chip area available to the genetic algorithm is studied.

Citation:

Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, "Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip," eh, pp.75, 2002 NASA/DoD Conference on Evolvable Hardware (EH'02), 2002

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