loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
The Third NASA/DoD Workshop on Evolvable Hardware
A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits
Long Beach, Cailfornia
July 12-July 14
ISBN: 0-7695-1180-5
Jorg Langeheine, Heidelberg University
Joachim Becker, Heidelberg University
Simon Foiling, Heidelberg University
Karlheinz Meier, Heidelberg University
Johannes Schemmel, Heidelberg University
Abstract: This paper describes and discusses an intrinsic approach to hardware evolution of analog electronic circuits using a Field Programmable Transistor Array (FPTA). The FPTA is fabricated in a 0.6 μ.m CMOS process and consists of 16 x 16 transistor cells. The chip allows to configure the gate geometry as well as the connectivity of each of the 256 transistors. Evolutionary algorithms are to be run on a commercial PC to produce the new circuit configurations that are downloaded to the chip via a PCI card. In contrast to extrinsic hardware evolution all environmental conditions present on the device under test have to be taken into account by the evolutionary algorithm. Thus a selection pressure is raised towards solutions that actually work on real dice.
Citation:
Jorg Langeheine, Joachim Becker, Simon Foiling, Karlheinz Meier, Johannes Schemmel, "A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits," eh, pp.0172, The Third NASA/DoD Workshop on Evolvable Hardware, 2001
Usage of this product signifies your acceptance of the Terms of Use.