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The Second NASA/DoD Workshop on Evolvable Hardware (EH'00)
Self-Repairable EPLDs: Design, Self-Repair, and Evaluation Methodology
Palo Alto, California
July 13-July 15
ISBN: 0-7695-0762-X
Chong H. Lee, Portland State University
Marek A. Perkowski, Portland State University
Douglas V. Hall, Portland State University
David S. Jun, Portland State University
This paper describes the concept of self-testable and self-repairable EPLDs (Electrically Programmable Logic Devices) for high security and safety applications. A design methodology is proposed for self-repairing of a GAL (Generic Array Logic) which is a kind of EPLD. Our fault-locating and fault-repairing architecture uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair all multiple stuck-at faults, which might occur on E 2 CMOS cells in programmable AND plane. A “column replacement” method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that the self-repairable GAL will last longer in the field.
Citation:
Chong H. Lee, Marek A. Perkowski, Douglas V. Hall, David S. Jun, "Self-Repairable EPLDs: Design, Self-Repair, and Evaluation Methodology," eh, pp.183, The Second NASA/DoD Workshop on Evolvable Hardware (EH'00), 2000
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