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The First NASA/DOD Workshop on Evolvable Hardware
The MorphoSys Dynamically Reconfigurable System-on-Chip
Pasadena, California
July 19-July 21
ISBN: 0-7695-0256-3
ASCII Text
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Guangming Lu, Hartej Singh, Ming-hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M.C. Filho, Vladimir Castro Alves, "The MorphoSys Dynamically Reconfigurable System-on-Chip," Evolvable Hardware, NASA/DoD Conference on, pp. 152, The First NASA/DOD Workshop on Evolvable Hardware, 1999.
 
 
BibTex
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@article{ 10.1109/EH.1999.785447,
author = {Guangming Lu and Hartej Singh and Ming-hau Lee and Nader Bagherzadeh and Fadi J. Kurdahi and Eliseu M.C. Filho and Vladimir Castro Alves},
title = {The MorphoSys Dynamically Reconfigurable System-on-Chip},
journal ={Evolvable Hardware, NASA/DoD Conference on},
volume = {0},
year = {1999},
isbn = {0-7695-0256-3},
pages = {152},
doi = {http://doi.ieeecomputersociety.org/10.1109/EH.1999.785447},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Evolvable Hardware, NASA/DoD Conference on
TI - The MorphoSys Dynamically Reconfigurable System-on-Chip
SN - 0-7695-0256-3
SP
EP
A1 - Guangming Lu,
A1 - Hartej Singh,
A1 - Ming-hau Lee,
A1 - Nader Bagherzadeh,
A1 - Fadi J. Kurdahi,
A1 - Eliseu M.C. Filho,
A1 - Vladimir Castro Alves,
PY - 1999
VL - 0
JA - Evolvable Hardware, NASA/DoD Conference on
ER -
 
Guangming Lu, University of California at Irvine
Hartej Singh, University of California at Irvine
Ming-hau Lee, University of California at Irvine
Nader Bagherzadeh, University of California at Irvine
Fadi J. Kurdahi, University of California at Irvine
Eliseu M.C. Filho, Federal University of Rio de Janeiro
Vladimir Castro Alves, Federal University of Rio de Janeiro
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platform for the evolvable hardware(EH) simulation with the help of the software.
Citation:
Guangming Lu, Hartej Singh, Ming-hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M.C. Filho, Vladimir Castro Alves, "The MorphoSys Dynamically Reconfigurable System-on-Chip," eh, pp.152, The First NASA/DOD Workshop on Evolvable Hardware, 1999
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