Abstract: A fundamental requirement for hard real-time systems is the knowledge of tasks worst case execution times (WCET). Static worst-case execution time analysis (WCET analysis), thanks to the static analysis of a piece of source code, returns an upper bound of the time required to execute it on a given hardware. Taking into account modern architectural features makes it possible to determine tight WCET bounds. Several mechanisms that use modeling and simulate some architectural feature behaviors such as instruction cache, branch prediction mechanism and pipeline have been proposed in the literature. These methods have often been designed independently from each other, which leads to an integration issue. This paper proposes to formalize (through data structures) three techniques for static simulation of instruction cache, pipeline and branch prediction in order to gather them in an integrated static WCET analysis framework. Performance improvements due to the integrated approach are also given.