The functional validation of a state-of-the-art reconfigurable computing system design is usually a laborious, ad-hoc and open-ended task. It can be accomplished through two basic approaches: simulation and formal verification. In validation using a formal verifcation approach, it attempts to establish that the Register Transfer Level (RTLJ design synthesized from the algorithmic behavioral specification is mathematically correct. Therefore, finding the verification methods to provide accurate andfast validation easily would be very useful. In this paper. we develop a semantics based on a Partial Order Based Model (POM) for RTL and. through this semantics, propose a formal verification method to prove the correctness of the RTLsynthesis result. This method can be used to achieve the following. On one hand, it can accurately verify en RTL description with respect to a behavioral specifcation of the system; on the other hand, it can decide whether twoprocesses, which are supposed to implement the samefunction, have the same interactive behaviors so that one can be replaced by the other.