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7th IEEE International Conference and Workshop on the Engineering of Computer Based Systems
A Choice of SM/DM Parallel ANN Implementation for Embedded Applications
Edinburgh, Scotland
April 03-April 07
ISBN: 0-7695-0604-6
ASCII Text
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Vaclav Dvorak, Rudolf Cejka, "A Choice of SM/DM Parallel ANN Implementation for Embedded Applications," Engineering of Computer-Based Systems, IEEE International Conference on the, pp. 18, 7th IEEE International Conference and Workshop on the Engineering of Computer Based Systems, 2000.
 
 
BibTex
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@article{ 10.1109/ECBS.2000.839857,
author = {Vaclav Dvorak and Rudolf Cejka},
title = {A Choice of SM/DM Parallel ANN Implementation for Embedded Applications},
journal ={Engineering of Computer-Based Systems, IEEE International Conference on the},
volume = {0},
year = {2000},
isbn = {0-7695-0604-6},
pages = {18},
doi = {http://doi.ieeecomputersociety.org/10.1109/ECBS.2000.839857},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Engineering of Computer-Based Systems, IEEE International Conference on the
TI - A Choice of SM/DM Parallel ANN Implementation for Embedded Applications
SN - 0-7695-0604-6
SP
EP
A1 - Vaclav Dvorak,
A1 - Rudolf Cejka,
PY - 2000
KW - Performance modeling/prediction
KW - prototyping parallel programs
KW - parallel implementations of neural networks
VL - 0
JA - Engineering of Computer-Based Systems, IEEE International Conference on the
ER -
 
Vaclav Dvorak, Brno University of Technology
Rudolf Cejka, Brno University of Technology
This paper examines implementations of a multi-layer perceptron (MLP) on bus-based shared memory (SM) and on distributed memory (DM) multiprocessor systems. The goal has been to optimize HW and SW architectures in order to obtain the fastest response possible. Prototyping parallel MLP algorithms for up to 8 processing nodes with the DM as well as SM memory was done using CSP-based TRANSIM tool. The results of prototyping MLPs of different sizes on various number of processing nodes demonstrate the feasible speedups, efficiency and time responses for the given CPU speed, link speed or bus bandwidth.
Index Terms:
Performance modeling/prediction, prototyping parallel programs, parallel implementations of neural networks
Citation:
Vaclav Dvorak, Rudolf Cejka, "A Choice of SM/DM Parallel ANN Implementation for Embedded Applications," ecbs, pp.18, 7th IEEE International Conference and Workshop on the Engineering of Computer Based Systems, 2000
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