High Level Testbench Generation for VHDL Models

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Stanislaw Deniziak Articles by Krzysztof Sapiecha

IEEE Conference and Workshop on Engineering of Computer-Based Systems

Nashville, Tennessee

March 07-March 12

ISBN: 0-7695-0028-5

	ASCII Text	x
	Stanislaw Deniziak, Krzysztof Sapiecha, "High Level Testbench Generation for VHDL Models," Engineering of Computer-Based Systems, IEEE International Conference on the, pp. 146, IEEE Conference and Workshop on Engineering of Computer-Based Systems, 1999.

	BibTex	x
	@article{ 10.1109/ECBS.1999.755873, author = {Stanislaw Deniziak and Krzysztof Sapiecha}, title = {High Level Testbench Generation for VHDL Models}, journal ={Engineering of Computer-Based Systems, IEEE International Conference on the}, volume = {0}, year = {1999}, isbn = {0-7695-0028-5}, pages = {146}, doi = {http://doi.ieeecomputersociety.org/10.1109/ECBS.1999.755873}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Engineering of Computer-Based Systems, IEEE International Conference on the TI - High Level Testbench Generation for VHDL Models SN - 0-7695-0028-5 SP EP A1 - Stanislaw Deniziak, A1 - Krzysztof Sapiecha, PY - 1999 KW - testbench KW - VHDL KW - simulation. VL - 0 JA - Engineering of Computer-Based Systems, IEEE International Conference on the ER -

Stanislaw Deniziak, Cracow University of Technology

Krzysztof Sapiecha, Cracow University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ECBS.1999.755873

In this paper, a new technique of automatic generation of VHDL testbenches is presented. Testbenches are generated using stimuli description in the WEGA language [16] and VHDL entity declaration of the model under test. This technique makes it possible to reduce the length and complexity of testbenches by the factor of 10, on average. Moreover, describing testbenches in WEGA is much easier and flexible than describing them directly in VHDL. The source WEGA code is also more readable.

Index Terms:

testbench, VHDL, simulation.

Citation:

Stanislaw Deniziak, Krzysztof Sapiecha, "High Level Testbench Generation for VHDL Models," ecbs, pp.146, IEEE Conference and Workshop on Engineering of Computer-Based Systems, 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.