Evaluating architectural design decisions early in the design process is critical for cost effective design. Formal analysis can provide such evaluation if architectures are defined in a formal way. This paper describes how VSPEC can be used to formally define an architecture during requirements specification. VSPEC is a Larch interface language for VHDL that annotates VHDL entities using the axiomatic style provided by Larch interface languages. Using VHDL's structural definition support, entities described in this manner are connected to form architectural descriptions. Activation conditions over component inputs define when that component must perform its transform. In this paper, we formally define a VSPEC component's state and how component states interact in an architecture. A rudimentary formal semantics for component activation is presented and used to define two potential satisfaction criterion.