A Codesign Case Study: Implementing Arithmetic Functions in FPGA's

E
ECBS
1996
IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96)
Abstract - A Codesign Case Study: Implementing Arithmetic Functions in FPGA's

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IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96)

Friedrichshafen, GERMANY

March 11-March 15

ISBN: 0-8186-7355-9

	ASCII Text	x
	I.V. Klotchkov, S. Pedersen, "A Codesign Case Study: Implementing Arithmetic Functions in FPGA's," Engineering of Computer-Based Systems, IEEE International Conference on the, pp. 389, IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996.

	BibTex	x
	@article{ 10.1109/ECBS.1996.494565, author = {I.V. Klotchkov and S. Pedersen}, title = {A Codesign Case Study: Implementing Arithmetic Functions in FPGA's}, journal ={Engineering of Computer-Based Systems, IEEE International Conference on the}, volume = {0}, year = {1996}, isbn = {0-8186-7355-9}, pages = {389}, doi = {http://doi.ieeecomputersociety.org/10.1109/ECBS.1996.494565}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Engineering of Computer-Based Systems, IEEE International Conference on the TI - A Codesign Case Study: Implementing Arithmetic Functions in FPGA's SN - 0-8186-7355-9 SP EP A1 - I.V. Klotchkov, A1 - S. Pedersen, PY - 1996 KW - Codesign KW - FPGA KW - Case Study KW - Design Methods KW - Arithmetic Functions VL - 0 JA - Engineering of Computer-Based Systems, IEEE International Conference on the ER -

I.V. Klotchkov, Technical University of Denmark

S. Pedersen, Technical University of Denmark

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ECBS.1996.494565

Different way of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. This also includes a comparison of four different design methods.The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware.The conclusion is that by adding one relatively simple board containing two FPGA's in the prototype setup, the total computing time is reduced by 30 %. The total amount of image data, in this case 300 Mbyte which has to be transmitted via network, is reduced by a factor of two, and the required network bandwidth is reduced similarly.

Index Terms:

Codesign, FPGA, Case Study, Design Methods, Arithmetic Functions

Citation:

I.V. Klotchkov, S. Pedersen, "A Codesign Case Study: Implementing Arithmetic Functions in FPGA's," ecbs, pp.389, IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

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