Euromicro Symposium on Digital System Design (DSD'04) Evaluation of Transient Fault Susceptibility in Microprocessor Systems Rennes, France August 31-September 03 ISBN: 0-7695-2203-3
The paper addresses the problem of evaluating transient fault impact on COTS microprocessor systems. We present the problem of fault effect propagation from low logical to software and application levels. Such an analysis is needed to optimize error detection and correction mechanisms at hardware and software levels. For this purpose we use sophisticated fault injectors. The usefulness of the presented approach was proved in many experiments described in the paper. It may support hardware/software co-design.
Citation:
P. Gawkowski, J. Sosnowski, "Evaluation of Transient Fault Susceptibility in Microprocessor Systems," dsd, pp.432-439, Euromicro Symposium on Digital System Design (DSD'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||