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Euromicro Symposium on Digital System Design (DSD'04)
The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data
Rennes, France
August 31-September 03
ISBN: 0-7695-2203-3
A. Drozd, Odessa National Polytechnic University, Ukraine
R. Al-Azzeh, Zarqa Private University, Jordan
J. Drozd, Odessa National Polytechnic University, Ukraine
M. Lobachev, Odessa National Polytechnic University, Ukraine
In this paper we present logarithmic checking method for on-line testing of the fixed-point adder, multiplier and divider for processing of the approximated data. The check code as logarithmic estimation of fixed-point number is defined. Check equations, connected check codes of operands and result for operation of addition multiplication and division are proved. The method distinguishes errors, which are essential and non-essential for reliability of calculated results. It allows to lower rejection of authentic results and to raise results check reliability in processing of the approximated data in comparison with the residue checking.
Citation:
A. Drozd, R. Al-Azzeh, J. Drozd, M. Lobachev, "The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data," dsd, pp.416-423, Euromicro Symposium on Digital System Design (DSD'04), 2004
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