This paper presents a high speed, non-pipelined FPGA implementation of the Rijndael Algorithm [AES Proposal: Rijndael, AES algorithm submission], which has been selected as the new AES Algorithm [Draft FIPS for the AES] by the National Institute of Standards and Technology (NIST) [National Institute of Standards and Technology]. In this study, we have implemented both the encryption and the decryption algorithms of Rijndael on the same FPGA. All the key and data length combinations of the original Rijndael Algorithm are supported. This implementation, which uses 8378 slices and 4 Block RAM's of the Xilinx FPGA, has a worst case operating frequency of 65 MHz, yielding a maximum throughput of 1.19 Gb/s.