Parallel Turbo Decoder architectures have recently been proposed to reach high-throughput channel decoding capacity. However, the implementation of the underlying parallel interleaving subsystem suffers from memory access conflicts; those translate into logic overhead and critical path issues which are blocking factors for handheld System-on-Chip solutions. In this paper, we explore several architecture and VLSI design strategies that drastically reduce the logic overhead and data-path delays of concurrent interleaving architectures. A novel stalling mechanism is introduced that reduces the interleaving subsystem die area and improves the architecture scalability with respect to the number of MAP producers. ASIC synthesis results in 0.18μm and 0.13μm CMOS STMicroelectronics technologies demonstrate the efficiency of the proposed VLSI concurrent interleaving architecture.