The architecture of a simple and networkable data-driven processor is demonstrated. The processor uses computational data-flow graphs as its programming model, in which functional processing nodes exhibit data dependencies among each other to execute instructions. The nature of the program execution method differs from a conventional processor, which uses a program counter to sequence instructions. The processor is also micro- threaded, in which a single processor can support many nodes, and selects the node to be processed on a cycle-by-cycle basis depending on the availability of data for the node. This data-driven processor consists of a dual-port memory that stores instructions and data, an ALU, and a controller. The flexible architecture allows processors to be grouped in the form of clusters dedicated for certain mathematical functions. Furthermore, clusters can be networked with other clusters for multi-tasking operations. All processors are identical in architecture except for their ALU, which is "tuned" for better performance at different tasks during a networked operation.