Euromicro Symposium on Digital Systems Design (DSD'03) A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications Belek-Antalya, Turkey September 01-September 06 ISBN: 0-7695-2003-0
In this paper, we present an architecture and a hardware implementation of the 2-D Discrete Wavelet Transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n1 \times n2 image processed using (n1/k1) \times (n2/k2) sized tiles the latency is equal to the time elapsed to accumulate a (1/k1) portion of one image. In addition, a (2/k1) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003.
Citation:
O. Benderli, Y. ?. Tekmen, N. Ismailoglu, "A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications," dsd, pp.384, Euromicro Symposium on Digital Systems Design (DSD'03), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||