A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator

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	Similar Articles Articles by M. Bera Articles by G. Danese Articles by I. De Lotto Articles by F. Leporati Articles by A. Spelgatti

Euromicro Symposium on Digital Systems Design (DSD'03)

Belek-Antalya, Turkey

September 01-September 06

ISBN: 0-7695-2003-0

	ASCII Text	x
	M. Bera, G. Danese, I. De Lotto, F. Leporati, A. Spelgatti, "A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator," Digital Systems Design, Euromicro Symposium on, pp. 173, Euromicro Symposium on Digital Systems Design (DSD'03), 2003.

	BibTex	x
	@article{ 10.1109/DSD.2003.1231922, author = {M. Bera and G. Danese and I. De Lotto and F. Leporati and A. Spelgatti}, title = {A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-2003-0}, pages = {173}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231922}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator SN - 0-7695-2003-0 SP EP A1 - M. Bera, A1 - G. Danese, A1 - I. De Lotto, A1 - F. Leporati, A1 - A. Spelgatti, PY - 2003 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

M. Bera, Universit? di Pavia

G. Danese, Universit? di Pavia

I. De Lotto, Universit? di Pavia

F. Leporati, Universit? di Pavia

A. Spelgatti, Universit? di Pavia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231922

Exploiting hardware devoted to a specific application requires a proper programming support, like libraries allowing a simple interface with the device. As a complementary design, a dedicated device language might be developed to make its programming easier. In previous works [1][2] we presented the architecture of a floating point operations accelerator based on Field Programmable Gate Array (FPGA) technology. In this paper we describe the development environment which allows to write, translate and simulate instruction sequences written in a language specifically conceived and designed for that device.

Citation:

M. Bera, G. Danese, I. De Lotto, F. Leporati, A. Spelgatti, "A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator," dsd, pp.173, Euromicro Symposium on Digital Systems Design (DSD'03), 2003

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