In this paper we present a methodology for a low-power branch identification mechanism, which enables the design of extremely power efficient branch predictors for embedded processors. The proposed technique utilizes application-specific information regarding the control-flow structure of the program major loops. Such information is used to completely eliminate the power hungry Branch Target Buffer (BTB) lookups which normally occur at every execution cycle. Exact application knowledge regarding the control-flow structure of the program obviates the power expensive BTB operations, thus enabling the utilization of contemporary branch predictors in high-end, yet power-sensitive embedded processors. The utilization of exact application knowledge results not only in the complete elimination of the power hungry BTB structure but also in a perfect branch and target address identification. A cost-efficient and programmable hardware architecture for capturing the control-flow structure of the program is presented thereafter. The hardware complexity of the proposed architecture is carefully analyzed in terms of power, performance and area overhead. The proposed technique delivers power reductions in excess of 90% for a set of embedded benchmarks.