The actual operation of a complementary metal-oxide- semiconductor (CMOS) gate driving long resistance - inductance - capacitance (RLC) interconnects is investigated in this paper. Using the alpha-law model, inductance effects of long on-chip interconnects on the operating region of submicron CMOS line-driver transistors are analysed. A computationally efficient closed form expression for the time the MOS transistors of a line driver actually operate in the saturation region is also presented. The accuracy of the novel expression, particularly suitable for CAD tools implementation, is within 15% as compared to SPICE simulations for a wide range of line parameters.