Fault injection techniques are increasingly used when designing a circuit, in order to analyze the potential cases in which a fault could lead to an application failure. In most experiments, such failures were simply defined as erroneous responses of the circuit. However, in many cases, an erroneous response does not necessarily lead to a failure at the application level, even when the discrepancy with the nominal behavior has a long duration. An accurate but high-level modeling of the complete system is therefore required to discriminate real failure conditions from non-critical errors.On the opposite, performing fault injections on a very high level modeling of the circuit functions does not allow a designer to analyze the effect of real faults potentially occurring in the field, such as bit-flips in internal registers. Injections must therefore be performed using a RT level (or lower level) modeling of the circuit, connected to the system-level modeling of the environment.This paper presents an approach for such mixed-level dependability analyses and reports on a case study.