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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)
Exploiting an I-IP for In-Field SOC Test
Cannes, France
October 10-October 13
ISBN: 0-7695-2241-6
P. Bernardi, Politecnico di Torino, Italy
M. Rebaudengo, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
Today's complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly designed for test, are coupled with functional IPs both to obtain yield improvement during the manufacturing process and to perform volume production test. In this paper, a new test control schema based on the use of an Infrastructure IP (I-IP) is proposed for the test on-site of SoCs. The proposed in-field test strategy is based on the ability of a single I-IP to periodically monitor the behavior of the system by reusing the test structures introduced for manufacturing test. The feasibility of this approach has been proved for SoCs including microprocessors and memories equipped with P1500 compliant solutions. Experimental results highlight the advantages in term of reusability and scalability, low impact on system availability and reduced area overhead.
Citation:
P. Bernardi, M. Rebaudengo, M. Sonza Reorda, "Exploiting an I-IP for In-Field SOC Test," dft, pp.404-412, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004
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