19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)
At-Speed Functional Verification of Programmable Devices
Cannes, France
October 10-October 13
ISBN: 0-7695-2241-6
In this paper we present a novel approach for functional verification of programmable devices. The proposed methodology is suited to refine the results obtained by a functional Automatic Test Pattern Generator (ATPG). The hard-to-detect faults are examined by exploiting the controllability ability of a high-level ATPG in conjunction with the observability potentiality of software instructions targeted to the programmable device. Generated test programs can be used for both functional verification and at-speed testing.
Citation:
Nicola Bombieri, Franco Fummi, Graziano Pravadelli, "At-Speed Functional Verification of Programmable Devices," dft, pp.386-394, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004