Simulation based fault injection is widely used in order to validate fault tolerant digital circuits with respect to transient faults (TFs). The size of circuits often requires the use of cycle based (accurate) register transfer level (RTL) simulation, which, however, does not account for the timing of the functional units. In this paper, TFs affecting memory elements are annotated by using the timing of the driven combinational logic. Such annotation can be used to increase the accuracy of cylce based RTL fault simulation. This analysis is performed without the need to perform event driven fault simulation, its results show that relevant errors may be in order in case the IC's timing is neglected. The accuracy of the proposed technique has been validated by comparing its results with those of event driven simulation.