19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04) Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories Cannes, France October 10-October 13 ISBN: 0-7695-2241-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.43
Nonvolatile repair caches require less area than traditional row, column, or block redundancy schemes, to repair random defective memory cells in deep submicron embedded SRAMs and new nonvolatile memories such as FeRAM, MRAM, and OUM. Small memories with few defects can be repaired efficiently in real time by the direct mapped nonvolatile repair cache whereas large memories with many defects can be repaired more effectively and in real time by the N way set associative repair cache. An 8 way set associative repair cache was implemented in the Texas Instruments-Agilent Technologies 64Mbit FeRAM chip.
Citation:
John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk, "Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories," dft, pp.347-355, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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