19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04) Toggle-Masking for Test-per-Scan VLSI Circuits Cannes, France October 10-October 13 ISBN: 0-7695-2241-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.61
This paper presents a novel toggle-masking technique that eliminates the switching activity in a circuit under test (CUT) during the scan-shifting in a test-per-scan test. Conventional scannable D flip-flops (DFFs) are modified to ensure that CUT inputs remain unchanged until an entire test vector is loaded, significantly reducing the power dissipation in the CUT. Our experiments on IS-CAS85/89 benchmark circuits show that the proposed technique offers an average of 47% savings in average power compared to previous work in [Minimized Power Consumption for Scan-Based BIST], and an average of 99% savings in average power and 8% savings in peak power with respect to test-per-scan circuits with conventional DFFs.
Citation:
Nitin Parimi, Xiaoling Sun, "Toggle-Masking for Test-per-Scan VLSI Circuits," dft, pp.332-338, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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