First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique

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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique (PDF)

Cannes, France

October 10-October 13

ISBN: 0-7695-2241-6

	ASCII Text	x
	S. Bhunia, H. Mahmoodi, A. Raychowdhury, K. Roy, "First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 314-315, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004.

	BibTex	x
	@article{ 10.1109/DFT.2004.32, author = {S. Bhunia and H. Mahmoodi and A. Raychowdhury and K. Roy}, title = {First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2004}, issn = {1550-5774}, pages = {314-315}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2004.32}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique SN - 1550-5774 SP314 EP315 A1 - S. Bhunia, A1 - H. Mahmoodi, A1 - A. Raychowdhury, A1 - K. Roy, PY - 2004 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

S. Bhunia, Purdue University, IN

H. Mahmoodi, Purdue University, IN

A. Raychowdhury, Purdue University, IN

K. Roy, Purdue University, IN

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.32

This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Instead of using an extra latch as in the enhanced scan method, we propose using supply gating at the first level of logic gates to hold the state of the combinational circuit. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 27% in area overhead with an average improvement of 62% in delay overhead and 87% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

Citation:

S. Bhunia, H. Mahmoodi, A. Raychowdhury, K. Roy, "First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique," dft, pp.314-315, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004

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