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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)
A New Approach to Linear Connections Building BIST Structure Based on CSTP Structure
Cannes, France
October 10-October 13
ISBN: 0-7695-2241-6
Ireneusz Gosciniak, University of Silesia in Katowice, Poland
The paper presents a method to build testing structure of single- and multi- modular circuits. The presented method is based on creating of linear connections which build the testing structure of circuit equipped with CSTP structure, composed of boundary scan path elements. The results of investigations testify efficiency of the method. The discussion on influence of different modifications of CSTP structure on work efficiency was made. The method discussed in the paper can become the alternative in relation to method which separates internal self-testing paths.
Citation:
Ireneusz Gosciniak, "A New Approach to Linear Connections Building BIST Structure Based on CSTP Structure," dft, pp.256-263, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004
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