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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines
Cannes, France
October 10-October 13
ISBN: 0-7695-2241-6
Irith Pomeranz, Purdue University, W. Lafayette, IN
Sudhakar M. Reddy, University of Iowa, Iowa City
We describe a method to reduce the fault latency, i.e., the time it takes to detect a fault after it occurs, during concurrent on-line testing. A high fault latency can negatively affect the fault coverage in various ways. The fault latency is reduced by using what we call checking functions. A checking funtion cf_i expresses the function of a line g_i in the circuit as a function of one or more other lines. During concurrent on-line testing, the value of g_i is compared to the value of cf_i. A mismatch indicates the presence of a fault. The advantage of checking functions is that they only use lines that already exist in the circuit. We demonstrate that benchmark circuits have large numbers of checking functions to choose from. We also demonstrate the increase in fault coverage and the reductions in fault detection times possible by using checking functions.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines," dft, pp.183-190, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004
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