Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code

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	Similar Articles Articles by Sobeeh Almukhaizim Articles by Yiorgos Makris

18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)

Boston, Massachusetts

November 03-November 05

ISBN: 0-7695-2042-1

	ASCII Text	x
	Sobeeh Almukhaizim, Yiorgos Makris, "Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 563, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.

	BibTex	x
	@article{ 10.1109/DFTVS.2003.1250156, author = {Sobeeh Almukhaizim and Yiorgos Makris}, title = {Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {563}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250156}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code SN - 1063-6722 SP EP A1 - Sobeeh Almukhaizim, A1 - Yiorgos Makris, PY - 2003 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Sobeeh Almukhaizim, Yale University

Yiorgos Makris, Yale University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250156

We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check codes and duplication in order to not only perform error detection but also provide diagnosis and correction capabilities. Informed selection among the outputs of the original synthesized circuit and the outputs of a constrained-sharing resynthesized duplicate with parity check codes renders a low-cost fault tolerant design. Experimental results con.rm the efficacy of the proposed method as a general solution for designing fault tolerant circuits.

Citation:

Sobeeh Almukhaizim, Yiorgos Makris, "Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code," dft, pp.563, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003

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