18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
Today?s System on Chip (SoC) designs can use hundreds of embedded memories. Most of these are created by automated generators, which must produce a wide variety of configurations while retaining essential capabilities in area, performance, power and testability. Redundancy, repair, and test issues in the context of memory generators are more complex than they are in the context of individual embedded memories, or even internally developed memories.
Citation:
Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker, "Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator," dft, pp.467, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003