loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
M. Nicolaidis, iRoC Technologies
N. Achouri, iRoC Technologies
L. Anghel, TIMA laboratory
This paper presents the architecture of a new memory Built-In Self-Repair approach targeting memories affected by high defect densities (several orders of magnitude higher than in current technologies). Such repair scheme is suitable for building memories in nano-technologies, which are subject to very high defect densities. The new approach allows combining two defected units to create a fault-free unit. For making this combination possible, the approach analyses the polarities of the errors produced by the faulty units of the memory, and combines units producing the same error polarities. The combination is done by means of functions that mask the errors of a particular polarity.
Citation:
M. Nicolaidis, N. Achouri, L. Anghel, "A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities," dft, pp.459, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.