18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Fault Tolerant Hopfield Associative Memory on Torus
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
The associative Hopfield memory is a very useful Artificial Neural Network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an efficient and fault tolerant algorithm for implementing the Hopfield ANN on torus parallel architecture. The main advantage of this algorithm is fault tolerance, high performance, and cost effectiveness. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube without the added cost; it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. Moreover, the developed algorithm has an added advantage over other known algorithms due to its fault tolerance feature, which is based on ABFT techniques. The main advantage of our ABFT method over other existing ABFT methods is its ability to detect and correct several faults without any additional hardware overhead (i.e. no extra row or column is needed).
Citation:
R. A. Ayoubi, H. A. Ziade, M. A. Bayoumi, "Fault Tolerant Hopfield Associative Memory on Torus," dft, pp.369, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003