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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
ASCII Text
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A. Ammari, R. Leveugle, M. Sonza-Reorda, M. Violante, "Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 336, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.
 
 
BibTex
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@article{ 10.1109/DFTVS.2003.1250129,
author = {A. Ammari and R. Leveugle and M. Sonza-Reorda and M. Violante},
title = {Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2003},
issn = {1063-6722},
pages = {336},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250129},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels
SN - 1063-6722
SP
EP
A1 - A. Ammari,
A1 - R. Leveugle,
A1 - M. Sonza-Reorda,
A1 - M. Violante,
PY - 2003
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
A. Ammari, TIMA Laboratory
R. Leveugle, TIMA Laboratory
M. Sonza-Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
Methods allowing a designer to perform early dependability analyses aim either at classifying the faults according to their main potential effect, or at analyzing more in depth the error propagation paths in the circuit. In the two cases, these methods can be applied at several description levels, starting from the behavioral level down to the gate level with back-annotation data. This paper compares results obtained at RT and gate levels. The advantages of combining an error propagation path analysis and a classification are also discussed.
Citation:
A. Ammari, R. Leveugle, M. Sonza-Reorda, M. Violante, "Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels," dft, pp.336, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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