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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Quadruple Time Redundancy Adders
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
ASCII Text
x 
 
Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander, Jr., "Quadruple Time Redundancy Adders," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 250, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.
 
 
BibTex
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@article{ 10.1109/DFTVS.2003.1250119,
author = {Whitney J. Townsend and Jacob A. Abraham and Earl E. Swartzlander, Jr.},
title = {Quadruple Time Redundancy Adders},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2003},
issn = {1063-6722},
pages = {250},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250119},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Quadruple Time Redundancy Adders
SN - 1063-6722
SP
EP
A1 - Whitney J. Townsend,
A1 - Jacob A. Abraham,
A1 - Earl E. Swartzlander, Jr.,
PY - 2003
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Whitney J. Townsend, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
Earl E. Swartzlander, Jr., University of Texas at Austin
This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Tripple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% - 55% reduction in hardware complexity while incurring a reasonable delay increase.
Citation:
Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander, Jr., "Quadruple Time Redundancy Adders," dft, pp.250, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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