This paper presents a linear matrix driven scan based test methodology for ASIC designs which, compared to conventional scan methodology, reduces the test application time as well as the required tester memory and test data by an order of magnitude - without deteriorating the test quality. The proposed test methodology uses a linear matrix to drive a large number of parallel scan chains from a small set of chip pins. A multi-input-signature-register (MISR) is used at the output of chains to compress the test output response. By increasing the number of parallel scan chains, the length of the chains is reduced, which directly impacts the number of test cycles required to shift test data through the chains. This allows one to considerably reduce the test application time required for shifting data through scan chains. It also reduces the test data required to be stored in tester memory, thus, considerably reducing the manufacturing test cost, and allowing the reuse of older generation of less expensive testers with smaller memory.