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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
ATE-Amenable Test Data Compression with No Cyclic Scan
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
Hamidreza Hashempour, Northeastern University
Fabrizio Lombardi, Northeastern University
This paper deals with a novel data compression technique for Automatic Test Equipment (ATE). A new correlation extraction technique is presented which allows spanning the compressed test data over the memory of multiple ATE channels. After reordering, vector processing is executed on a columnwise basis such that bits in the same position of all vectors are simultaneously provided to each pin of the head. Differentiation which is commonly used to extract correlation among vectors is not required in the proposed technique. Several ATE issues related to memory utilization, off-chip compression/decompression, decompression circuitry area overhead (inclusive of the area of the Cyclic-Scan-Register, CSR), and the entropy of test data (as figure of merit for correlation extraction) are analyzed. Experimental results for combinational and sequential benchmark circuits are presented to substantiate the validity of the proposed technique for an ATE environment.
Citation:
Hamidreza Hashempour, Fabrizio Lombardi, "ATE-Amenable Test Data Compression with No Cyclic Scan," dft, pp.151, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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