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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
On the Test and Diagnosis of the Perfect Shuffle
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
L. Schianoand, Northeastern University
F. Lombardi, Northeastern University
In this paper, a new structural approach is proposed for the full diagnosis (with no aliasing and confounding) of shorts and stuck-at faults in the interconnect of a perfect shuffle. This approach utilizes graph coloring techniques to generate a test set based on the adjacencies in the largest necklace of the shuffle. The conditions for no aliasing and confounding as well as fault detection are presented at function of the largest short fault. For detecting stuck-at faults it is shown that a constant number of tests is required. A test generation algorithm with quadratic execution complexity in the size of the shuffle is proposed. This algorithm generates a test set which diagnoses a perfect shuffle of size N with no aliasing and confounding 0(log2(log2(N))) tests. The application of these results to multistage interconnection networks (MINs) is also presented; MINs can be constructed by cascading perfect shuffles and are characterized by switching operation. It is shown that constant testability of MINs can be still achieved for diagnosis under fault models which preserve the loop properties of the necklaces in a perfect shuffle.
Citation:
L. Schianoand, F. Lombardi, "On the Test and Diagnosis of the Perfect Shuffle," dft, pp.97, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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