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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Level-Hybrid Optoelectronic TESH Interconnection Network
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
Vijay Jain, University of South Florida
Glenn Chapman, Simon Fraser University
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors or devices, it permits efficient VLSI/ULSI realization, it is designed to make use of redundancy for defect circumvention, and it appears to be well suited for 3-D stacked implementation. Here, we discuss a novel extension to these capabilities through the provision of optical interconnections at the highest level, while keeping the lower levels electronic through metal wires. The advantages of the resulting architecture, dubbed as Level-Hybrid Optoelectronic TESH, are the elimination of bottlenecks which typically occur at the highest level due to the aggregation of traffic, and the reduction of cost by using traditional wire channels at the lower levels -- where optical links are deemed unnecessary.
Citation:
Vijay Jain, Glenn Chapman, "Level-Hybrid Optoelectronic TESH Interconnection Network," dft, pp.45, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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