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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
ASCII Text
x 
 
X. Wang, M. Ottavi, F. Lombardi, "Yield Analysis of Compiler-Based Arrays of Embedded SRAMs," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 3, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.
 
 
BibTex
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@article{ 10.1109/DFTVS.2003.1250089,
author = {X. Wang and M. Ottavi and F. Lombardi},
title = {Yield Analysis of Compiler-Based Arrays of Embedded SRAMs},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2003},
issn = {1063-6722},
pages = {3},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250089},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Yield Analysis of Compiler-Based Arrays of Embedded SRAMs
SN - 1063-6722
SP
EP
A1 - X. Wang,
A1 - M. Ottavi,
A1 - F. Lombardi,
PY - 2003
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
X. Wang, Northeastern University
M. Ottavi, Northeastern University
F. Lombardi, Northeastern University
This Paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.
Citation:
X. Wang, M. Ottavi, F. Lombardi, "Yield Analysis of Compiler-Based Arrays of Embedded SRAMs," dft, pp.3, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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