1999 International Symposium on Defect and Fault Tolerance in VLSI Systems Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction Albuquerque, New Mexico November 01-November 03 ISBN: 0-7695-0325-X
In order to meet the power and reliability constraints, it is important to reduce average power and peak power during test. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG), which can be used during on-line testing of large circuits requiring low power dissipation.The LPATPG can be implemented by linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by finding the best initial conditions in the CA cells.Results on ISCAS benchmark circuits show that average power reduction of up to 79.7%, peak power reduction of up to 39.2% and energy reduction of up to 84.4% can be achieved (compared to linear cellular automata) while achieving high fault coverage.
Index Terms:
BIST Synthesis, Low Power, Testing, Peak Power, Weighted Random Pattern Generator, Cellular Automata, Low Power BIST
Citation:
Xiaodong Zhang, Kaushik Roy, "Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction," dft, pp.148, 1999 International Symposium on Defect and Fault Tolerance in VLSI Systems, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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