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Second IEEE International Workshop on Electronic Design, Test and Applications
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design
Perth, Australia
January 28-January 30
ISBN: 0-7695-2081-2
ASCII Text
x 
 
N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, V. Mahalingam, T. L. Rajaprabhu, "Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 333, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004.
 
 
BibTex
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@article{ 10.1109/DELTA.2004.10067,
author = {N. Venkateswaran and V. Barath Kumar and R. Raghavan and R. Srinivas and S. Subramanian and V. Balaji and V. Mahalingam and T. L. Rajaprabhu},
title = {Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design},
journal ={Electronic Design, Test and Applications, IEEE International Workshop on},
volume = {0},
year = {2004},
isbn = {0-7695-2081-2},
pages = {333},
doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10067},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Electronic Design, Test and Applications, IEEE International Workshop on
TI - Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design
SN - 0-7695-2081-2
SP
EP
A1 - N. Venkateswaran,
A1 - V. Barath Kumar,
A1 - R. Raghavan,
A1 - R. Srinivas,
A1 - S. Subramanian,
A1 - V. Balaji,
A1 - V. Mahalingam,
A1 - T. L. Rajaprabhu,
PY - 2004
KW - Cross-talk fault
KW - Power awareness
KW - Berger encoding
KW - Adaptive Huffman compression
KW - Memory refetches
VL - 0
JA - Electronic Design, Test and Applications, IEEE International Workshop on
ER -
 
The advent of DSM technology and multi-GHz operation of processors has increased the severity of cross-talk faults. Even with many preventive solutions like cross-talk driven routing, power supply shielding and intentional skewing; cross-talk faults cannot be completely avoided. In this paper we present an enhanced power aware fault tolerant pipelined architecture - xIDAC/E. In our earlier work - IDAC/E, compression and encoding were done on individual instructions whereas xIDAC/E operates on grouped instruction partitions. This offers higher compression efficiency due to repeatability and power reduction due to lesser memory accesses. Simulation results are provided with regard to instruction partitioning, their compression & encoding, and memory re-fetches. Analysis show this power reduction overcompensate the overheads due to partitioning, compression and encoding. The impact of encoding of address & data bus on fault tolerance and power is also provided.
Index Terms:
Cross-talk fault, Power awareness, Berger encoding, Adaptive Huffman compression, Memory refetches
Citation:
N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, V. Mahalingam, T. L. Rajaprabhu, "Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design," delta, pp.333, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004
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