Second IEEE International Workshop on Electronic Design, Test and Applications
On Using Test Vector Differences for Reducing Test Pin Numbers
Perth, Australia
January 28-January 30
ISBN: 0-7695-2081-2
Marie-Lise Flottes, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Regis Poirier, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
Bruno Rouzeyre, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier
We propose a method for reducing test data volume on System on Chip (SoC) architecture. This method reduces the required number of Automatic Test Equipment (ATE) output pins compared to the number of scan-in inputs on every core (horizontal compression). Compression and decompression are based on arithmetic operations and operators.
Citation:
Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre, "On Using Test Vector Differences for Reducing Test Pin Numbers," delta, pp.275, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004