On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure

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Second IEEE International Workshop on Electronic Design, Test and Applications

Perth, Australia

January 28-January 30

ISBN: 0-7695-2081-2

	ASCII Text	x
	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita, "On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 269, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004.

	BibTex	x
	@article{ 10.1109/DELTA.2004.10014, author = {Hiroyuki Yotsuyanagi and Toshimasa Kuchii and Shigeki Nishikawa and Masaki Hashizume and Kozo Kinoshita}, title = {On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2004}, isbn = {0-7695-2081-2}, pages = {269}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10014}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure SN - 0-7695-2081-2 SP EP A1 - Hiroyuki Yotsuyanagi, A1 - Toshimasa Kuchii, A1 - Shigeki Nishikawa, A1 - Masaki Hashizume, A1 - Kozo Kinoshita, PY - 2004 KW - null VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Hiroyuki Yotsuyanagi, Univ. of Tokushima

Toshimasa Kuchii, Sharp Corporation

Shigeki Nishikawa, Sharp Corporation

Masaki Hashizume, Univ. of Tokushima

Kozo Kinoshita, Osaka Gakuin University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10014

In this paper, a new method for reducing test application time of sequential circuits with scan design is proposed. Scan design is one of most popular design for testability techniques. To reduce scan shifts required to provide the scan pattern, a fully testable scan tree configuration is proposed. The method can configure scan trees before generating test vectors without degrading fault coverage by considering a circuit structure. In a fully testable scan tree, flip-flops are placed in parallel in case that they have no overlap in the set of the outputs connected from them. To reduce much scan shifts, a folding scan tree, which is configured based on a fully testable scan tree by placing more flip-flops in parallel, is also configured. Moreover, a scan tree configuration considering scan-out operation is also presented. Experimental results for benchmark circuits are shown.

Citation:

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita, "On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure," delta, pp.269, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004

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