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Second IEEE International Workshop on Electronic Design, Test and Applications
CMOS ADC with Reconfigurable Properties for a Cellular Handset
Perth, Australia
January 28-January 30
ISBN: 0-7695-2081-2
A. Stojcevski, Victoria University, Melbourne, Australia
J. Singh, Victoria University, Melbourne, Australia
A. Zayegh, Victoria University, Melbourne, Australia
A low power reconfigurable ADC architecture is described for a mobile terminal receiver. The architecture can automatically scale the resolution by monitoring in-band and out-of-band powers. The architecture performance was evaluated in a simulation UTRA-TDD environment. A power consumption analysis of the implemented architecture is also presented. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architecture can save an average of 74 percent power dissipation for TDD mode when compared to a fixed ADC word length of 16 bits. This will prolong talk and standby time in a mobile terminal.
Citation:
A. Stojcevski, J. Singh, A. Zayegh, "CMOS ADC with Reconfigurable Properties for a Cellular Handset," delta, pp.103, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004
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