Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits

D
DELTA
2002
The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Abstract - Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits

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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)

Christchurch, New Zealand

January 29-January 31

ISBN: 0-7695-1453-7

	ASCII Text	x
	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, "Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 431, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002.

	BibTex	x
	@article{ 10.1109/DELTA.2002.994665, author = {Yoshinobu Higami and Shin-ya Kobayashi and Yuzo Takamatsu}, title = {Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2002}, isbn = {0-7695-1453-7}, pages = {431}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994665}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits SN - 0-7695-1453-7 SP EP A1 - Yoshinobu Higami, A1 - Shin-ya Kobayashi, A1 - Yuzo Takamatsu, PY - 2002 KW - CMOS circuit KW - Power dissipation KW - Test generation KW - Fault simulation VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Yoshinobu Higami, Ehime University

Shin-ya Kobayashi, Ehime University

Yuzo Takamatsu, Ehime University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994665

This paper presents a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Test vectors are modified by inverting values of primary inputs one by one. With respect to the reduction of power dissipation, we check if the average number of signal transition gates is decreased and if the maximum number of signal transition gates is not increased. Original fault coverage is guaranteed by logic simulation and fault simulation. The effectiveness of the proposed method is shown by experimental results for ISCAS'89 benchmark circuits.

Index Terms:

CMOS circuit, Power dissipation, Test generation, Fault simulation

Citation:

Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, "Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits," delta, pp.431, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002

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