This paper examines the C-testability of a carry-free divider architecture that uses a radix-2 number system. This divider is extremely fast in comparison to the traditional carry-propagate method of division. It has a computational time of the order of O(W), while carry-propagate division has a time of the order of O(W2). The results of the investigation presented here show that the architecture requires the addition of a significant amount of logic circuitry for correct functionality and uniformity of the inputs and outputs. This paper presents the logic blocks required to turn the architecture into one that can be implemented in hardware and examines the effects of these changes on the computation time and testability.