GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor

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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)

Christchurch, New Zealand

January 29-January 31

ISBN: 0-7695-1453-7

	ASCII Text	x
	Victor Varshavsky, Vyacheslav Marakhovsky, "GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor," Electronic Design, Test and Applications, IEEE International Workshop on, pp. 73, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002.

	BibTex	x
	@article{ 10.1109/DELTA.2002.994592, author = {Victor Varshavsky and Vyacheslav Marakhovsky}, title = {GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor}, journal ={Electronic Design, Test and Applications, IEEE International Workshop on}, volume = {0}, year = {2002}, isbn = {0-7695-1453-7}, pages = {73}, doi = {http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994592}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Electronic Design, Test and Applications, IEEE International Workshop on TI - GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor SN - 0-7695-1453-7 SP EP A1 - Victor Varshavsky, A1 - Vyacheslav Marakhovsky, PY - 2002 KW - Asynchronous Design KW - GALA - Globally Asynchronous Locally Arbitrary KW - Counterflow Pipeline Processor KW - Arbitration KW - Synchronous Prototype VL - 0 JA - Electronic Design, Test and Applications, IEEE International Workshop on ER -

Victor Varshavsky, Neural Networks Technologies Ltd.

Vyacheslav Marakhovsky, The University of Aizu

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994592

This paper approaches the problem of building an asynchronous control for a stage of the Sproull's Counterflow Pipeline Processor (CFPP) that does not need arbiters. It is shown that there is no arbitration situations in a synchronous pipeline control circuit with two-track synchronization. An asynchronous control circuit can be built by a synchronous prototype with help of GALA-methodology using the procedure of synchro-stratum designing we suggested earlier.

Index Terms:

Asynchronous Design, GALA - Globally Asynchronous Locally Arbitrary, Counterflow Pipeline Processor, Arbitration, Synchronous Prototype

Citation:

Victor Varshavsky, Vyacheslav Marakhovsky, "GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor," delta, pp.73, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002

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