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Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04)
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
ASCII Text
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F. Menichelli, M. Olivieri, L. Benini, M. Donno, L. Bisdounis, "A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design," Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp. 30312, Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04), 2004.
 
 
BibTex
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@article{ 10.1109/DATE.2004.1269256,
author = {F. Menichelli and M. Olivieri and L. Benini and M. Donno and L. Bisdounis},
title = {A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {3},
year = {2004},
issn = {1530-1591},
pages = {30312},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269256},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
SN - 1530-1591
SP
EP
A1 - F. Menichelli,
A1 - M. Olivieri,
A1 - L. Benini,
A1 - M. Donno,
A1 - L. Bisdounis,
PY - 2004
KW - null
VL - 3
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
F. Menichelli, University of Rome "La Sapienza"
M. Olivieri, University of Rome "La Sapienza"
L. Benini, University of Bologna
M. Donno, Bulldast s.r.l
L. Bisdounis, Intracom S.A.
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results.
Citation:
F. Menichelli, M. Olivieri, L. Benini, M. Donno, L. Bisdounis, "A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design," date, vol. 3, pp.30312, Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04), 2004
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